Binary inverter circuit employing field effect transistors



M. E. SEKELY Nov. 2, 1965 BINARY INVERTER CIRCUIT EMPLOYING FIELD EFFECT TRANSISTORS Original Filed June 22, 1960 I F .f. m,

5 Sheets-Sheet 1 a a W a 5m 8 4 Kr M n. M

l M w; M w

m I 74 1 U M W 2 f I w. J O

46 J 0102') our ATTOAA/E) m m w.

Ma a E JZ/(HY 22 CIN Nov. 2, 1965 M. E. SEKELY 3,215,851

BINARY INVERTER CIRCUIT EMPLOYING FIELD EFFECT TRANSISTORS Original Filed June 22, 1960 5 Sheets-Sheet 2 FIOM mar 007F117 48 Fed/l4 $04! 007707 36 may am'r 515mm? sun 007/1/7' are 01/7 +25% M126 r 190 I i196 i W 205 .210 212 {19 g E J diff) 01/7 IN VEN TOR. Xw h IM/CHAEZ 15 fimzr B Y an?? M. E. SEKELY Nov. 2, 1965 BINARY INVERTER CIRCUIT EMPLOYING FIELD EFFECT TRANSISTORS 5 Sheets-Sheet 3 Original Filed June 22, 1960 SIG/V41 INVENTOR. MCHAEL 5 5574 62) ATTOAIVE) United States Patent 3 215,861 BINARY INVERTER CIRCUIT EMPLOYING FIELD EFFECT TRANSISTORS Michael E. Sekely, Belle Mead, N.J., assiguor to Radio Corporation of America, a corporation of Delaware Original application June 22, 1960, Ser. No. 37,940, ow Patent No. 3,100,838, dated Aug. 13, 1963. Divided and this application Nov. 28, 1962, Ser. No. 240,614

Claims. (Cl. 307-88.5)

This application is a division of application Serial No. 37,940, filed June 22, 1960, now Patent Number 3,100,838.

An object of the invention is to provide a new and improved logical inverter circuit.

The circuit of the invention includes two unipolar field effect transistors connected source electrode to drain electrode between an operating volt-age source and a point of reference potential. A first circuit applies a signal to the gate electrode of one of the transistors. A second circuit receives the signal from the sour-ce-to-drain electrode connection of said transistors and applies a feedback signal to the gate electrode of the other transistor.

The invention is described in greater detail in the drawings described briefly below and in the explanation following the drawing description:

FIG. 1 is a cross-sectional view of a unipolar transistor;

FIG. 2 is a schematic circuit diagram of a full adder circuit;

FIG. 3 is the circuit of FIG. 2 with the sum and carry portions of the circuit integrated into a single piece of semiconductor mate-rial;

FIG. 4 is a schematic diagram of the inverter of the present invention which may be used in the circuit of FIG. 2;

FIG. 5 is an integrated form of the circuit of FIG. 4;

vFIG. 6 is a schematic circuit diagram of another form of adder circuit in which the inverter of the invention is employed;

FIG. 7 is the circuit of FIG. 6 with the sum and carry portion-s integrated into a single piece of semiconductor material;

FIG. 8 is a schematic showing of a way in which printed circuit windings may be connected to various electrodes of an integrated adder;

FIG. 9 shows another form of inverter which .may be used in integrated full adders;

FIG. 10 is .a schematic diagram of a modified unipolar transistor-resistor circuit; and

FIG. 11 is a schematic diagram of the carry circuit of a full adder integrated with the invertercircuit of the invention.

The circuits to be discussed in detail below all include unipolar transistors as active elements. These elements are described in an article by Wallmark and Marcus appearing in the IRE Transactions on Electronic Computers, June 1959, page 98, and elsewhere in the literature. Accordingly, only a brief description is given of the element and its mode of operation.

FIG. 1 is a schematic showing of a unipolar transistor. The body includes a P-type region and an N-type region. Charge carriers (electrons in the present case) flow from the source electrode 10 through the N-type material to the drain electrode .12. The N-ty-pe material includes a portion 14 of restricted cross-section known as the chan- See nel. Voltages applied to the gate electrode 16 change the eifective cross-section of the channel 14 thereby altering its impedance and controlling the current fiow from the source to the drain electrode 12. As pointed out in reference 3 in the article above (Dacey and Ross, Unipolar Field EtTect Transistor, Proc. IRE, vol. 41, No. 8, pp. 970-979, August 1953 the mechanism by which the conductivity of the current path (the channel) between the source and drain electrodes is controlled is a transverse electric field due to the control \(gate) voltage. For this reason, the generic term field effect transistor is also often employed to describe transistors operating on this general principle.

In the transistor illustrated, as the reverse bias on the gate electrode 16 is increased (the gate electrode made more negative), the drain current flow decreases. A family of characteristics of current versus voltage for a typical unipolar transistor appears in FIG. 2 of the Wallmark et al. article above.

The circuits to be discussed are computer circuits and all operate on binary information. An input representing one binary digit causes the transistor to conduct heavily. An input representing the other binary digit causes the transistor to be substantially cut off. A voltage V applied to the gate electrode 16 of sufficient amplitude to drive the unipolar transistor to cut-01f is normally known as the pinch-oft voltage W The supply voltage should be equal to or greater than W and of opposite sign to W The region of which the channel 14 is formed may be either of N or P-type material. Transistors of the former type, hereafter termed N-type transistors, are shown clear in the other figures of the drawings and transistors of the latter type, hereafter termed P-type transistors, are shown cross-hatched in the drawings.

The circuit shown in FIG. 2 is a full adder. The following convention is adopted for this circuit. A binary zero input is a voltage suificient to cut-oil the transistor, that is, the pinch-ofi? voltage W for the transistor. The N-type transistors shown normally have supply voltages equal to IW of the order of +15 volts or greater so that the zero input for most N-type transistors may be of the order of 15 volts or W,,. A binary one input may be of the order of -W 3 or 5 volts and this permits the transistor to conduct heavily. (Transistors 32 and 46 (at the bottom left of the figure) are designed somewhat difierently as is explained in more detail later.) A zero output for the N-type transistors of FIG. 2 is of the order of +15 volts and a one output for these transistors is of the order of a few volts positive.

Three input voltages are applied to the full adder of FIG. 2. The first is an addend voltage legended X applied to terminal 18; the second is an augend voltage lengended Y applied to terminal 20; and the third is a carry voltage legended C applied to terminal 22. The circuit includes a terminal 24 to which a source of operating voltage ;+W for the N-type transistors may be applied and a terminal 26 to which a source of operating voltage W for the P-type transistor may be applied. A first pair of transistors 28 and 30 are connected in shunt and a third transistor 32 is connected in series with the shunt circuit. These three transistors are connected through a load resistor 34 to terminal 24.

The sum output terminal 36 is connected to junction 38 between the load resistor 34 and transistors 28 and 30. Three transistors 40, 42 and 44 are connected in series between the sum output terminal 36 and ground. A third series circuit between sum output terminal 36 and ground includes transistor 40, transistor 46, and transistor 32. Transistors 32 and 46 are designed to have a pinch-off voltage W /3. The reason is that when transistor 62 conducts, the voltage drop across the transistor reduces the value of the negative voltage available to drive transistors 32 and 46 to cut-off.

The second output may be obtained from the circuit at carry output terminal 48. Transistors t) and 52 are connected in series between terminal 48 and ground. A pair of transistors 54 and 56 are connected in shunt with each other and a third transistor 58 is connected in series with the shunt circuit. The three transistors 54, 56 and 58 are connected between the carry output terminal 48 and ground. The carry output voltage is inverted by a stage 60, shown in a dashed block, and applied as an input to a number of the unipolar transistors in the sum .circuit. The specific inverter illustrated consists of a P-type unipolar transistor 62 in series with a resistor 64. The series circuit is connected between terminal 26 and ground.

' The truth table for the full adder of FIG. 2 is as Equations 1 and 2 can be manipulated to give the following:

S=(X+Y+C )U +XYC (1a) C =XY+YC +XC (2a) The circuit of FIG. 2 implements Equations 1a and 2a above. This can be seen by substituting for the XY and C terms, terms with subscripts which represent the transistors in FIG. 2. For the sum portion of the circuit:

S 28 o32 3 0 032 142 o46 o32 1" 140 42 44 which may be simplified to S: 2s+ so-iitzf osz-iunz mo For the carry portion of the circuit:

52 50+ 5s a+ s4 15a Some examples of the circuit operation for different assumed inputs are as follows. Assume first that the three inputs are all zero. This means that a voltage equal to the pinch-off voltage or about 15 volts is applied to input terminals 18, and 22. Transistors 50 and 52 are both cut-ofi since +15 volts is applied from terminals 18 and 20 to their gate electrodes. Similarly, transistors 54, 56 and 58 are cut off since a pinch-off voltage is applied from terminals 18, 20 and 22 to their gate electrodes. Thus, a voltage of approximately +15 volts appears at the junction 66 between load resistor 68 and transistor 50. This junction is connected to the carry output terminal 48 so that +15 volts or binary zero appears at output terminal 48.

The +15 volts at junction 66 is applied via lead 70 to the gate electrode of transistor 62. This voltage is sufficient to drive transistor 62 to cut-01f so that junction 72 between load resistor 64 and transistor 62 is at substantially ground voltage. This voltage is applied to the gate electrodes of transistors 46 and 32 so that the latter are in condition to conduct.

The pinch-off voltage on terminals 18 and 20 is applied to the gate electrodes of transistors 28 and 30 so that these two transistors are cut-ofi. Input terminal 22 is connected via lead 74 to the gate electrode of transsistor 40 so that transistor 40 is cut-off. Transistors 42 and 44 are connected to terminals 20 and 18, respectively, so that these two transistors are cut-off. Accordingly, even though transistors 32 and 46 are enabled, there is no conduction through any transistor path between junction 38 and ground and substantially +15 volts (binary zero) appears at sum output terminal 36.

Assume now that the X input is binary one (5 volts) and the Y and C inputs are each binary zero or 15 volts. This should give a sum output of one and a carry output of zero. Referring to FIG. 2, the binary one input applied to the gate of transistor 52 enables transistor 52 but since transistor 50 is cut-off, the series circuit does not conduct. In a similar manner transistor 54 is enabled by the binary one input but since the transistor 58 in series with it is cut-off, the circuit including transistor 58 and transistor 54 does not conduct. Accordingly, there is no conducting circuit between the carry output terminal 48 and ground and a binary zero (+15 volts) appears at the carry output terminal 48.

As already discussed, when the carry output is binary zero, transistors 32 and 46 are enabled. The binary one applied to the gate electrode of transistor 28 enables this transistor so that now both transistors 28 and 32 are enabled and current flows through load resistor 34 and these two transistors. The voltage at junction 38 now drops to a few volts positive and this voltage appears at sum output terminal 36. Thus, a binary one appears at the sum output terminal 36.

The last example to be given of the circuit operation is all inputs binary one. Now transistors 50 and 52 both conduct so that junction 66 drops from +15 volts to a few volts positive and a binary one output appears at carry output terminal 48. When a binary one appears at the carry output terminal, P-type transistor 62 is rendered conductive and it applied a sufiiciently negative voltage to N-type transistors 32 and 46 to cut them 011. However, the three binary one inputs turn on transistors 40, 42 and 44 so that a conductive path appears between the sum output terminal and ground. Accordingly, the voltage of this terminal drops from +15 volts to a few volts positive and a binary one output appears at the sum output terminal 36.

The circuit operation for other inputs is readily traced and is found to give the results shown in the truth table above.

The full adder of FIG. 2 includes 12 N-type unipolar transistors, one P-type unipolar transistor, and three resistors, a total of 16 elements. It has been found possible to integrate this circuit into two pieces of semiconductor material hereafter termed two sticks. The circuit is shown in FIG. 3. The transistors in the sticks are integrated in series, that is, drain-to-source, source-to-source, or drain-to-drain. All of the N-type transistors and the two load resistors for the sum and carry circuits are integrated into a single stick 80, and the inverter, consisting of the P-type transistor 62 and its load resistor, is in a second stick 82. The fabrication of the integrated transistor assembly, sometimes known as DCUT (direct coupled unipolar transistors) is described in the literature (see the article above and the references quoted therein). The drain of one transistor forms a continuation of the source of the next adjacent transistor or of the drain of the next adjacent transistor. Similarly, the source of one transistor is a continuation of the drain or source of the next transistor. One method of fabrication is to form grooves such as 84 in the P-type material of the gate region of suflicient depth to extend through the junction thereby providing active element-active element isolation. However, the direct connection from source to drain electrode provides the necessary ohmic coupling. Other methods of fabrication are also possible.

It is not necessary to describe the operation of the circuit of FIG. 3 as it is exactly the same as the circuit of FIG. 2. Similar reference numerals have been applied to similar elements. It might be pointed out that the resistors of FIG. 3 are actually transistors to which no gate electrode input signal is applied. The gate may be disconnected as shown in some of the figures or it may be tied to the drain electrode of one of the active unipolar transistors for which the resistor-unipolar transistor serves as a load resistor as shown in FIG. 10. The resistance of the resistor unipolar transistor is, in general, dependent upon the channel cross-section and may be made any practical value desired. However, for a given channel cross-section, the average value of transistor resistance may be decreased by connecting the resistor as shown in FIG. 10. This is advantageous as it increases the circuit speed and may be used in the circuits of FIGS. 2, 3, 6 or 7.

A practical circuit according to FIG. 3 may have the following dimensions: .140 x .020" and .04" x .0 sticks of .001" to 0.005" thickness.

In some applications in which it is desired to incorporate the full adder of FIG. 3 on a micro-miniature wafer .310 X .310" x .01", the single stick of FIG. 3 may be divided into two sticks. In this event the stick is preferably broken between resistors 34 and 68 or at the source connection of one resistor.

In the full adder of FIG. 2, the carry output is inverted and applied to some of the stages 32 and 46 of the sum circuits. The inverter shown consists of a unipolar transistor in series with a resistor. The voltage drop across the unipolar transistor (62 in FIG. 2) is such that the transistors 32 and 46 which receive the inverted carry must be designed to have a lower pinch-01f voltage -W 3) than the other transistors in the sum and carry circuits. This requires that the channel for transistors 32 and 46 be of smaller cross-section than the channels for'the other transistors. Other circuits may be used. A preferred type of inverter, according to the present invention, herein is shown in FIG. 4. A full adder using this circuit can employ unipolar transistors which all require the same pinch-off voltage. The circuit includes, rather than a unipolar transistor and resistor, two active unipolar transistors 90 and 92. These are connected in series. The upper transistor 90 receives its input from the carry output terminal 48. The terminal 96 between the .two transistors is connected to the gate electrode of one or more transistors in the sum circuits. One such transistor 98 is shown. The output of transistor 98 is connected via feedback connection 100 to the gate electrode of transistor 92. The power supply voltage for transistors 90 and 92 is somewhat higher than that employed in the circuit of FIG. 2. The voltage may, for example, be 4/3 W,,.

The circuit of FIG. 4 operates as follows. Assume first that the input to the gate electrode of transistor 90 is a binary zero or volts. This drives transistor 90 towards cut-01f so that the terminal 96 between transistors 90 and 92 is driven in the positive direction, that is, from a negative value towards ground. Terminal 96 is connected to the gate electrode of transistor 98 and the positive going voltage applied to the gate electrode causes transistor 98 to conduct more heavily. When this occurs, the output of transistor 98 is driven in the negative direction, that is, it is driven from a more positive value toward ground. This output is coupled via lead 100 to the gate electrode of transistor 92 and tends to cause transistor 92 to conduct more heavily. Summarizing the operation, the positive voltage applied to transistor 90 causes its impedance to increase and the feedback voltage which 6 results, which is applied to transistor 92, causes the impedance of transistor 92 to decrease. The overall effect then is to drive point 96 toward ground. Neither transistors nor 92 cut-off during the process.

When a binary one (a voltage a few volts positive) is applied to the gate electrode of transistor 90, transistor 90 tends to conduct heavily. This makes terminal 96 more negative and this negative voltage applied to the gate electrode of transistor 98 causes the latter to be driven toward cut-off. The feedback voltage which results becomes more positive and this causes transistor 92 to tend to be driven toward cut-off. In summary then, a binary one applied to transistor 90 causes the impedance of transistor 90 to decrease and the impedance of transistor 92 to increase so that terminal 96 between the two transistors becomes negative to the extent of about W or 15 volts. Again, neither transistor 90 nor transistor 92 is cut-off in the process.

The circuit of FIG. 4 may be integrated as shown in FIG. 5. Similar reference numerals primed are applied to similar elements.

Another possible inverter for the circuit of FIG. 2 (or the one of FIG. 6) is a battery such as shown in FIG. 9. The battery floats and for a circuit like the one of FIG. 2 may have a voltage of about 20 volts. When the carry output of the circuit is binary zero 15 volts), the output voltage of the inverter 60 applied to the gate electrode of transistor 46 will be 5 volts or a binary one input to that transistor. Similarly, when the carry output is a binary one (say +5 volts or less), then the output voltage of the inverter is a binary zero or 15 volts or more. If an inverter such as shown in FIG. 9 is employed in the circuit of FIG. 2, transistors 46 and 32 may be identical with the other N transistors. In other words, these transistors may have pinch-off voltages of -W just like the other N-type transistors in the circuit.

In the circuit of FIG. 2, a binary zero input is W or about 15 volts and a binary one input is W /3 or about -5 volts. The circuit of FIG. 6 is the inverse of the one of FIG. 2. In other words, the binary zero input is -W 3 or -5 volts and the binary one input is W or 15 volts.

Referring to FIG. 6, the carry output circuits are quite similar to the analogous circuits in FIG. 2 and the same reference numerals plus 100 have been applied. The inversion circuit is similar to the one shown in FIG. 4 and again similar reference numerals plus 100 have been applied. The sum circuits include three transistors 202, 204 and 206 connected in series between the sum output terminal 136 and ground. It also includes three transistors 208, 210 and 212 connected in shunt and the shunt circuit connected in series with a fourth transistor 214. Transistor 214 and the shunt circuit are connected in series between the sum output terminal 136 and ground.

The truth table for the circuit of FIG. 6 is identical to the one for the circuit of FIG. 2. However, it should be remembered that now W represents a binary one input and -W 3 a binary zero input. Also, a binary zero output is represented by a few volts positive and a binary one output by +W (+15 volts).

The operation of the circuit of FIG. 6 is as follows. Assume first that the X, Y, and C inputs are all binary zero. Transistors and 152 conduct so that terminal 166 is a few volts positive and the carry output at terminal 148 is therefore binary zero. In like manner, transistors 202, 204 and 206 in the sum circuit conduct so that terminal 138 is at a few volts positive and a binary zero output appears at sum output terminal 136.

Assume now that the X input is binary one and the Y and C inputs are binary zero. Transistor 154 in the carry circuit is driven to cut-off and transistors 158 and 156 which are connected to the C and Y inputs respectively conduct so that current flows from terminal 166 through transistors 156 and 158. Accordingly, terminal 166 has a voltage of a few volts positive and the carry output is binary zero.

Transistor 190 in the inverter stage receives the binary zero output and produces at terminal 196 a binary one output. This binary one output is applied to transistor 214 and drives this transistor to cutoff. Accordingly, no current flows from terminal 138 through transistor 214. Transistor 202 is also driven to cut-off by the'binary one input. Accordingly, no current flows through transistors 202, 204 and 206. The result is that terminal 138 becomes positive to the extent of approximately W or +15 volts and a binary one appears at terminal 136.

Assume now that the X and Y inputs are both binary one and the C input is a binary zero. Transistors 150 and 152 which receive the X and Y inputs are both driven to cut-off. Transistors 154 and 156 which also receive the X and Y inputs are both driven to cut-off. Accordingly, there is no conducting path from terminal 166 to ground and the carry output at terminal 148 approaches W or binary one. The binary one output is inverted by inverter stage 192 to a binary zero and transistor 214 is enabled. Transistor 212 which is in series with transistor 214 also conducts in response to the binary zero input thereto from terminal 122. Accordingly, there is a conducting path from terminal 138 through transistors 214 and 2 12 and terminal 138 is at a voltage of a few volts positive. The sum output terminal therefore represents binary zero.

It is believed to beunnecessary to give added examples. This circuit may be traced for any combination of inputs to produce the desired full adder outputs, as given in the truth table above.

The circuit of FIG. 6 may be integrated into two sticks in the manner shown in FIG. 7. Like reference numerals have been applied to like circuit elements so that no further explanation is deemed necessary.

In the circuit discussed so far. the sum and carry circuits in the full adder are integrated into one stick of semiconductor material and the inverter for the carry output signal is a separate circuit. It is possible to integrate the inverter circuit into the same piece of semiconductor material as the carry circuit. This is shown in FIG. 11. Note that there is one more unipolar transistor, namely transistor 300, which is used. The operation of the circuit is the same as those already described and may be defined by the Boolean equation:

The topology is such that inverter 301, 302 (which is the same as the inverter of FIGS. 4 and 5) appears at the end of the stick. The integration of the transistors and resistor 303 is schematically illustrated by dashed arrow 304 which indicates the manner in which the transistors are serially connected.

In order to manufacture all unipolar elements on a single stick, a masking technique is employed. First the end on which the inverter is to be located of a stick of intrinsic material is masked and the N-type transistors are formed by diffusion and doping techniques. Then the N-type transistors are masked and the P-type are formed at the end of the stick by similar techniques.

FIG. 8 is an-abbreviated showing of how the integrated circuit may appear in practical form. The direct coupled transistors are shown at 220. The gate portions of the transistors are interconnected in any desired manner by a printed circuit shown at 222. The printed circuit is on an insulating supporting base shown at 224. The source and drain electrodes of the transistors may be interconnected in a similar manner by a second printed circuit on a second insulated backing neither of which is shown in the figure. The completed circuit may take the form of a sandwich consisting of a first printed circuit, the direct coupled unipolar transistors, and a second printed circuit, in that order.

What is claimed is:

1. Incombination, a pair of unipolar transistors con- Q U nected in series drain electrode to source electrode between an operating voltage source and a point of reference potential; a first circuit for applying a signal to the gate electrode of one of said transistors; a second circuit, including a third unipolar transistor, having an input terminal connected to receive a signal from the drain source electrode connection of said transistors, and having also an output terminal; and a feedback circuit from said output terminal to the gate electrode of the other of said transistors.

2. In combination, two terminals for receiving an operating voltage; first and second field-effect transistors formed of a common body of semi-conductor material, said first transistor connected at its drain electrode to one of said terminals and at its source electrode to the drain electrode of the second transistor, and the source electrode of the second transistor being connected to the other terminal; means for applying a signal to one of the transistors for changing its source-to-drain-electrode conductivity in one sense; and means coupled to said source-to-drain-electrode connection for applying a signal to the other transistor for changing the latters source-to-drain-electrode conductivity in the opposite sense. 3. In combination, two terminals for receiving an operating voltage; first and second field-effect transistors having channel regions of the same conductivity type, said first transistor connected at its drain electrode to one of said terminals and at its source electrode to the drain electrode of the second transistor, and the source electrode of the second transistor benig connected to the other terminal; means for applying a signal to the gate electrode'of one of the transistors for changing its source-to-drainelectrode conductivity in one sense; and means, including a field-effect transistor having a channel region of opposite conductivity type than that of the channel regions of the first and second transistors, coupled to said source-to-drain-electrode connection for applying a signal to the gate electrode of the other transistor, for changing the latters source-to-drainelectrode conductivity in the opposite sense. 4. In combination, two terminals for receiving an operating voltage; first and second field-effect transistors having channel regions of the same conductivity type, said first transistor connected at its drain electrode to one of said terminals and at its source electrode to the drain electrode of the second transistor, and the source electrode of the second transistor being connected to the other terminal; means for applying a signal to the gate electrode of one of the first and second transistors for changing its source-to-drain-electrode conductivity in one sense; a third field-effect transistor, having a channel region of opposite conductivity to that of the channel regions of the first and second transistors, connected at its gate electrode to the source-to-drain-electrode connection of the first and second transistors; and means coupled to the drain electrode of the third transistor for applying a signal to the other of the first and second transistors for changing the source-todrain-electrode conductivity of said other transistor in the opposite sense. 5. In combination, two terminals for receiving an operating voltage; first and second field-effect transistors having channel regions of the same conductivity type, said first transistor connected at its drain electrode to one of said terminals and at its source electrode to the drain electrode of the second transistor, and the source 9 l0 electrode of the second transistor being connected to References Cited by the Examiner me z i sfid r igiy ih g i signal to one of the transistors for UNITED STATES PATENTS changing its source-to-drain-e1ectrode conductivity in 0,576 1/56 camthers X one sense. and 5 3,005,937 10/61 Wallmark et a1 307-885 X 3,070,762 12/62 Evans 307-885 X means, including a field-effect transistor having a channel region of opposite conductivity type than that of 3135926 6/64 Bockemuehl 3307-18 X the channel regions of the first and second transistors, OTHER REFERENCES coupled to the source-to-drain-electrode connection Wallmark and Marcus; Integrated Devices Using of the first and Second transistors for pp y a 10 polar Transistor Logic, IRE Transactions on Electronic signal to the other of the first and second transistors, Computers, June 1959, pages 93 105 for changing said other transistors source-to-drainelectrode conductivity in the opposite sense. ARTHUR GAUSS, Primary Examiner- 

2. IN COMBINATION, TWO TERMINALS FOR RECEIVING AN OPERATING VOLTAGE; FIRST AND SECOND FIELD-EFFECT TRANSISTORS FORMED OF A COMMON BODY OF SEMI-CONDUCTOR MATERIAL, SAID FIRST TRANSISTOR CONNECTED AT ITS DRAIN ELECTRODE TO ONE OF SAID TERMINALS AND AT ITS SOURCE ELECTRODE TO THE DRAIN ELECTRODE OF THE SECOND TRANSISTOR, AND THE SOURCE ELECTRODE OF THE SECOND TRANSISTOR BEING CONNECTED TO THE OTHER TERMINAL; MEANS FOR APPLYING A SIGNAL TO ONE OF THE TRANSISTORS FOR CHANGING ITS SOURCE-TO-DRAIN-ELECTRODE CONDUCTIVITY IN ONE SENSE; AND MEANS COUPLED TO SAID SOURCE-TO-DRAIN-ELECTRODE CONNECTION FOR APPLYING A SIGNAL TO THE OTHER TRANSISTOR FOR CHANGING THE LATTER''S SOURCE-TO-DRAIN-ELECTRODE CONDUCTIVITY IN THE OPPOSITE SENSE. 